1. Technical Field
The present invention relates to a direct memory access apparatus and a direct memory access method.
2. Discussion of Related Art
Direct Memory Access (DMA) apparatus transmits data stored in memory independently from a processor and is widely used as a peripheral apparatus.
Generally, the direct memory access operation is used to move data block distributed with consecutive addresses such as a source address, a destination address and length field.
FIG. 1 is a block diagram for describing an operation of a direct memory access apparatus according to a conventional technique, and FIG. 2 is a block diagram for describing transmission operation of data line complicatedly distributed in memory according to a conventional technique.
As shown in FIG. 1, a main processor 100 determines a transmission rule in a memory 120 with which a direct memory access apparatus 110 will perform in an applied program through a source address 130, a destination address 140 and a transmission length 150. In case a trigger source of the transmission rule is determined (not shown), when a particular trigger source occurs, a transmission operation from the source address to the destination address is performed independently from the main processor. The direct memory transmission operation like this is effective to the transmission operation of data line distributed with a certain length and a certain interval or data line distributed in consecutive memories.
However, as shown in FIG. 2, an operation for transmitting data line distributed in memory with a nonuniform interval and/or a nonuniform length in a source memory space 200 and/or a destination memory space 210 is not capable of being transmitted with one time rule and requires a plurality of transmission rule serialized in the transmission of each data element and needs a frequent operation of the main processor. In addition, this conventional transmission operation causes frequent interruption to deteriorate an effect of the direct memory transmission. Meantime, when considering an operation with the main processor excluding the direct memory access apparatus, since the above complex memory access causes frequent cache miss, using the direct memory access apparatus is advantageous. Therefore, an operation which has rules of variable length decoding, hashing, an assignment of subcarrier in OFDMA and which is inappropriate by a simple block transmission requires a transmission by the direct memory access apparatus which is capable of sending data line of variable length and interval at one time setting.